Carrier current digital data transceiver

ABSTRACT

An ASK carrier current digital data transceiver for transparent transfer of data between a broadband communication port and a baseband port consists mainly of an integrated circuit with transmit/receive logic for providing the required transparency and the ability to sense a contending signal. The transmit/receive logic places the transceiver in the transmit mode only when the baseband port is pulled low externally and not internally. This provides &#34;listen-while-talk&#34; contention sensing when the baseband port is high.

BACKGROUND OF THE INVENTION

Microprocessors are finding increasing applications as intelligent control devices in the home as well as in industry. When a plurality of such microprocessors are interconnected by means of a common data bus, various protocols are used for orderly information transfer, such as described within U.S. patent application Ser. No. 561,483 filed 12-14-83 of E. K. Howell et al, which application is incorporated herein for purposes of reference.

When the common data bus includes a broadband communication bus, such as a power line communication bus which contains a modulated high frequency carrier signal along with the power frequency, transceivers are used which must be capable of converting the modulated carrier to baseband data for utilization by the microprocessor as well as converting the baseband data from the microprocessor to modulated carrier for transmission on the power line communication bus. State of the art transceiver devices require four terminals for interconnection with a microprocessor to provide input data, output data and control of the transmitter and receiver sections of the transceiver, and hence are not suitable for direct connection to a two-conductor baseband data bus. Such transceiver devices also exhibit a low impedance to the broadband terminals in both receive and transmit modes of operation, hence causing attenuation of the carrier signals when a plurality of transceivers are connected to a two-conductor broadband data bus.

A carrier current digital data transceiver requiring only two terminals for interconnection with a microprocessor or a baseband data bus is described within the aforementioned Howell et al application. The Howell et al transceiver is designed using discrete components which, although achieving excellent results in industrial applications, do not readily lend to miniaturization, such as when required to be used with home appliances connected to the power bus by wall outlets.

The carrier current digital data transceiver of the instant invention provides transparent interface function between broadband data and baseband data buses along with sufficient logic and impedance control to overcome all the aforementioned problems involved with several microprocessors along a common data bus. The selection of circuit elements and functions allows the transceiver to be fabricated within an integrated circuit in a compact and efficient configuration.

SUMMARY OF THE INVENTION

A carrier current digital data transceiver is designed for implementation within an analog integrated circuit for communication of data at 1000 bits per second via ASK 100% modulation, i.e., on-off keying, of a carrier frequency in the 100 to 200 kilohertz range. An open collector driver coupled with a NOR gate at the baseband input/output port allows "listen-while-talk" function. A dynamic limiter consisting of a variable transconductance amplifier, low pass filter and dual polarity peak comparator function to remove noise from the carrier signal prior to demodulation of the carrier. A tri-state power amplifier provides a low impedance to the broadband terminals in the transmit mode and a high impedance in the receive mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic representation of the transceiver c1rcuit according to the invention;

FIG. 2 is a circuit diagram of the external components external to the integrated circuit utilized within the transceiver circuit of FIG. 1;

FIG. 3 is a circuit diagram of the dynamic limiter within the transceiver circuit of FIG. 1;

FIG. 4 is a circuit diagram of the gated level detector within the transceiver circuit of FIG. 1;

FIG. 5 is a circuit diagram of the time domain band pass filter within the transceiver circuit of FIG. 1;

FIG. 6 is a circuit diagram of the level detector, fast integrator, dual slope integrator, comparator, hysteresis, I/O baseband driver and T/R control logic within the transceiver circuit of FIG. 1;

FIG. 7 is a circuit diagram of the gated power amplifier within the transceiver circuit of FIG. 1; and

FIGS. 8-10 are circuit diagram of the integrated circuit utilized within the transceiver circuit of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT TRANSCEIVER FUNCTION

The block diagram of FIG. 1 shows the main functions of the transceiver 10. The baseband I/O port 11 is a single terminal, referenced to the negative DC power supply bus, and is commonly connected through a resistor to a positive supply voltage of 5 V, for example. The baseband port voltage is normally high, corresponding to the absence of carrier at the broadband port, and may be pulled low by the internal open-collector driver 28 in response to presence of a carrier at the broadband I/O port 12, indicating data is received, or it may be pulled low externally, by any one of several digital devices, such as microprocessors suitably connected with similar open-collector drivers, thereby causing a carrier signal to be produced at the broadband port 12 for transmission.

The transmit/receive (T/R) control is obtained by a NOR gate 27 which produces high output level only when the baseband port 11 is pulled low externally. The NOR gate output disables the receiving path via inverter 26, line 35 and gated level detector 21 and enables a tristate power amplifier 25 which drives the broadband I/O port 12 with a carrier signal. Although the enable-disable function, line 35, is shown applied to level detector 21, the function can be applied to any of the functional elements 22, 23, 24, 32, 31 or 30 with proper circuit modification. When the baseband port 11 is high, the transceiver 10 is always in the receiving mode and is capable, therefore, of sensing another carrier signal on the broadband bus during that time. This logic technique provides the required transparency characteristic as defined within the aforementioned Howell et al application and the ability to sense a contending signal.

The broadband I/O port 12 consists of a pair of terminals, only one of which is shown, capacitively coupled to a high-frequency isolation transformer 13 having an inductive impedance of about 2000 ohms, open circuit. Clamping diodes within voltage surge suppressor 14 on the secondary of transformer 13 limit transient voltages to ±/5 volts. In the receive mode, the output impedance of power amplifier 25 is about 10,000 ohms. A wide-band filter 15 presents a 2000 ohm load to the isolation transformer 13 and couples carrier signals to the input amplifier 17 within dynamic limiter 16.

The input amplifier 17 comprises a variable transconductance amplifier which converts the carrier signal voltage to a signal current driving a parallel resonant L/C narrow-band filter 20 through a resistor R_(A). The sum of filter voltage plus voltage across R_(A) is sensed by a dual-polarity peak voltage comparator 19 which produces a feedback signal to control the transconductance of the amplifier 17, thereby limiting the L/C filter voltage to a fixed amplitude for all input signal voltages above the minimum.

A level detector 21, controlled by the T/R logic as earlier described, passes positive peaks of the filter voltage above 50% of the limited value. These peaks are converted to a square wave at 1/2 carrier frequency by a frequency divider flip-flop 22. The square wave is coupled through a highpass filter 23 to a time domain bandpass filter 24 which passes the square wave to its output if frequency is within the pass band and has no output otherwise. The output square wave of this filter is, in essence, rectified and filtered within a detector and fast integrator 32 which recovers the "modulation envelope" (rectangular wave) of the carrier.

In order to minimize the effects of high-amplitude impulse noise, the rectangular wave drives a dual-slope linear integrator 31 to provide a state recognition time (SRT) of about 330 microseconds. The integrated wave is applied to a comparator 30 which reproduces the rectangular wave, delayed by the SRT, without narrow "glitches". Hysteresis 29 is connected to the comparator reference input via line 39 as a second means of eliminating narrow pulses.

Finally, the delayed rectangular wave of baseband data is applied to the inverting open-collector driver 28 of the baseband I/O port 11 and to the T/R NOR gate 27.

If the baseband port 11 and the input of driver 28 are both low, indicating that an external device has pulled the baseband port low, the NOR gate 27 disables the gated level detector 21 which establishes a "nocarrier" condition in the filter 23, detector and integrator 32, and comparator 30, hence maintaining the baseband driver input terminal low. The NOR gate 27 also enables the two-stage power amplifier 25 which applies the sinusoidal L/C filter voltage to the isolation transformer 13 with a voltage gain of about 50. The L/C filter 20 is driven to a fixed amplitude by feedback through the dynamic limiter 16, thus establishing the amplitude, frequency and waveshape of the transmitted carrier signal. A current limiting resistor R_(B) protects the power amplifier from shortcircuit and high voltage transients. Output impedance of the power amplifier in the transmit mode is less than 10 ohms, including R_(B). When the power amplifier is disabled, its output impedance increases to 10,000 ohms. This provides minimal attenuation of carrier signal and thereby allows a large number of such transceivers to be connected to a common broadband bus.

THE TRANSCEIVER

The transceiver broadband I/O port terminals T₁, T₂ of FIG. 2 are connected across a pair of line conductors, or the line and neutral or ground and neutral conductors of a power line which carries modulated carrier communication signals. The baseband I/O port terminals T₃, T₄ are connected to an I/O port on a microprocessor thereby allowing transparent communication between the microprocessor and any other microprocessor connected to a like transceiver operating on the same power line. The baseband I/O port terminals T₃, T₄ can also be connected to a baseband data bus containing a plurality of microprocessors whereby any one of the microprocessors can gain control of the bus and transmit to all the other microprocessors on that baseband data bus and through the transceiver onto the power line, serving as a broadband data bus, to all of a plurality of remote microprocessors similarly connected to the baseband I/O port terminals of like transceivers.

FIG. 2 shows the external components and power supply circuitry used within the transceiver circuit 10 of FIG. 1 relative to the integrated circuit implementation 40 shown in FIG. 8 of all the components contained within a single chip and which will be described below in greater detail. The broadband I/O port 12 consists of terminals T₁, T₂ which couple signals with either the line to neutral, neutral to ground, or line to line connections of a power line communication system (not shown) through a small high voltage capacitor C₁ to transformer 13 which is a high frequency isolation transformer which presents a magnetizing impedance of 2000 ohms at carrier frequency to I/O port 12. While a single capacitor C₁ is shown, certain applications may require the use of two capacitors in series. A DC blocking capacitor C₂ couples the transformer through current limiting resistors R₁, R₂ to output pin B of the IC. Diodes D₁, D₂ protect the circuit from high voltage transients by limiting the transformer secondary voltage to +/-1/2 Vcc. The positive supply voltage Vcc comprises 9 volts DC and is applied to the IC pins D, E. The negative is applied to IC pins A, U. The dual terminals minimize cross-talk between the output stage and the other circuits in the IC. The paired IC terminals are connected to a single pin in the IC package. Resistors R₅ -R₈ are arranged in a resistive divider string to provide a reference voltage V_(R), applied to pin G, bypassed by capacitor C₃, at 1/2 Vcc. The divider also supplies a bias voltage 20 millivolts above V_(R) applied to pin L and a second bias voltage 600 millivolts above V_(R) applied to pin O.

DYNAMIC LIMITER

The input to the dynamic limiter 16, shown in FIG. 1, is the carrier signal output of the wideband filter 15, comprised of capacitors C₄, C₅, C₆ and resistors R₉, R₁₀ and R₁₁, referenced to V_(R) through resistor R₁₀ as shown in FIG. 3. Although wideband filter 15 is shown as an R/C filter, an L/C filter is advantageous in certain applications. Signal amplitude ranges from 2 millivolts to 2 volts. Since noise pulses may exceed +/-Vcc, the voltage of amplifier input IC pin H is limited by transistors Q₁ and Q₁₀₁ in order to avoid overdriving the variable transconductance amplifier 17.

The dynamic limiter 16 comprising variable transconductance differential amplifier 17 provides a high output impedance current drive to parallel resonant L/C filter circuit 20. The transconductance amplifier 17 comprises transistors Q₂ -Q₇ and Q₁₀₂ and Q₁₀₃ within the dynamic limiter circuit 16 shown in FIG. 3. Transistors Q₄ and Q₅ are connected as a differential amplifier with the input signal and DC reference voltage V_(R) applied to IC pin H, the base of Q₄, and with offset-correcting DC feedback from the output IC pin J applied through lowpass filter R₁₂, C₇ to IC pin I and the base of Q₅. Emitter current for this amplifier is supplied by resistors R₁₅ and R₁₆ from Vcc to IC pin F and current mirror Q₂ and Q₃. The differential current output IC pin J is obtained from Q₁₀₂ and Q₁₀₃ through current mirror Q₆ and Q₇. Amplifier output current drives the tuned circuit L₁, C₈, through a resistor R.sub. 13 in order to develop a voltage signal proportional to current, which is added to the voltage developed across the tuned circuit. This composite signal is applied to the dual-polarity peak detector 19 of FIG. 1 at IC pin J pursuant to developing a feedback signal to control the current gain of the amplifier 17.

Various operating currents within the IC are established by current I_(B) through resistor R₁₄ to pin S and transistor Q₆₃ shown in FIG. 8, wherein emitter follower transistor Q₆₄ supplies the base voltage V_(B) required to establish this current in Q₆₃ and also supplies V_(B) to the bases of all the other transistors within the IC to establish the same current magnitude I_(B). Capacitor C₁₆ in FIG. 2 provides a bypass of high frequencies at IC pin S and suppresses parasite oscillations.

Transistors Q₉ and Q₁₂ with internal resistors R₁ and R₄ form a differential comparator with emitter degeneration. Emitter current for this comparator is derived from bias voltage V_(B) applied to the base of Q₁₁ and reduced to 0.7 I_(B) by emitter resistor R₃. Collector currents of Q₉ and Q₁₂ are applied to a pair of Wilson current mirrors, Q₁₀₄, Q₁₀₅, Q₁₀₆ and Q₁₀₇, having a common output equal to two times the higher of the two collector currents from the comparator. When the collector currents are equal (0.35 I_(B)), the mirror output current is 0.7 I_(B). This output current is applied to the collector of transistor Q_(1O) which is driven by bias voltage V_(B) to sink I_(B). Hence, at balance, Q₁₀ is saturated, base current is limited by R₂, and no base drive is applied to Q₈. When the comparator is unbalanced by approximately 50 millivolts by a signal of either polarity at the base of Q₉, one of the two collector currents exceeds 0.5 I_(B) resulting in mirror output current in excess of I_(B) which pulls Q₁₀ out of saturation and drives the base of feedback transistor Q₈. This action causes Q₈ to bypass some of the amplifier emitter current supplied at IC pin F to current mirror Q₂ and Q₃. Resistors R₁₄, R₁₅ and R₁₆ and capacitors C₉ and C₁₀ control the frequency response of this gain control feedback path in order to obtain the desired transient response to step changes in carrier signal strength and noise impulses.

LEVEL DETECTOR

The limiter output signal developed across the L/C resonant circuit, consisting of variable inductance L₁ and capacitor C₈, is applied to IC pin K of the gated level detector 21 as shown in FIG. 4. Transistors Q₁₃ and Q₁₅ form a differential comparator of this signal with respect to a DC level on IC pin L 20 millivolts above the reference voltage V_(R). When positive signal voltage peaks exceed this threshold level, the output is driven by current mirror Q₁₀₈ producing a current in excess of I_(B), the current sinking capability of Q₁₇. Emitter current of 2 I_(B) for the comparator is produced by bias voltage V_(B) applied to the bases of Q₁₄ and Q₁₆, as well as sink Q₁₇, through resistor R₅. In the transmit mode, the transmit/rece1ve control logic drives the base of Q₁₈ positive, causing Q₁₈ collector current to pull down the base voltages on Q₁₄, Q₁₆, and Q₁₇, thereby disabling the level detector with no output voltage. Transistor Q₁₈ thus senses the function of inverter 26 of FIG. 1.

TIME DOMAIN BANDPASS FILTER

Additional frequency selectivity is provided by the time domain bandpass filter 24, shown in FIG. 5, which is an "ideal" filter with flat pass-band and infinite attenuation. This filter measures the period of alternate cycles of signal frequency and produces a fixed output signal only when the period fits within a prescribed time window. Since each period measurement is independent of prior events, the response is fast and not related to width of the pass-band.

Signal frequency is halved to produce a fixed amplitude square wave with a half-period equal to signal period as follows. The output of the gated level detector 21 of FIG. 4 drives, through emitter follower Q₂₁, a conventional master-slave flip-flop frequency divider comprised of transistors Q₁₉, Q₂₀, Q₂₂, Q₂₃ and resistors R₆₋₁₂. The square wave output of this frequency divider is obtained at the collector of Q₂₃.

Since this output can be left in either the high or the low state when the input signal ceases at the end of a carrier burst, and since the succeeding filter circuit requires a low input for zero signal, the frequency divider output must be coupled to the time domain filter 24 through a high-pass filter 23 as shown in FIG. 1. Transistors Q₂₄ and Q₂₅, with resistors R₁₃ and R₁₄ and capacitor C₁₁ connected to IC pin M provide this function within the time doma1n bandpass filter circuit 24 of FIG. 5. When flip-flop output transistor Q₂₃ is turned on, Q₂₄ discharges capacitor C₁₁ and Q₂₅ is off. When Q₂₃ is turned off, the output at its collector is high and is applied to the time domain filter through resistor R₁₄, and charges capacitor C₁₁ through resistor R₁₃. If R₂₃ stays off longer than about 12 microseconds, Q₂₅ is turned on and the time domain filter input is pulled low.

The time window between a time t₁ and a time t₂ for filter 24 is produced by adjusting R₁₇ to charge C₁₂ to reach 4.5 volts (V_(R)) at IC pin N in time t₁ and to reach 5.1 volts (V_(R) +0.6 V) in time t₂ after the input (collector of Q₂₅) goes low. The lower cutoff frequency is defined by t₂ and the upper cutoff frequency by t₁. The timing capacitor C₁₂ is discharged by Q₂₈ when input is high, or is discharged after t₂ by Q₂₉ and held discharged until Q₂₈ turns on. At time t₁, transistors Q₃₅, Q₃₇, Q₁₁₂, Q₁₁₃ and Q₃₈, arranged as a comparator, enable the setting of the output flip-flop Q₃₉ and Q₄₀, if the input goes high between t₁ and t₂ by comparing the voltage on C₁₂ with the reference voltage V_(R). At time t₂, C₁₂ voltage reaches the higher potential of IC pin O, transistors Q₃₂, Q₃₄, Q₁₁₀, and Q₁₁₁, also arranged as a comparator, set flip-flop Q₃₀ and Q₃₁, thereby turning on Q₂₉, discharging capacitor C₁₂, and removing the output enable produced by the comparator consisting of transistors Q₃₅ and Q₃₇. When input goes high, C₁₂ is discharged, flip-flop Q₃₀ /Q₃₁ is reset by Q₂₆, and output flip-flop Q₃₉ /Q₄₀ is set by Q₂₇ and Q₄₁ if enabled by Q₃₈, that is, if between t₁ and T₂. When input goes low, C₁₂ is allowed to charge, and the output flip-flop is reset. Emitter currents for all the comparators and supply currents for the two flip-flops are provided by Q₃₃ and Q₃₆ driven at bias voltage V_(B) to produce current I_(B). The output flip-flop Q₃₉ /Q₄₀ drives output transistor Q₄₂ to provide inversion and current asymmetry for the fast-integrating level detection function.

DETECTOR, INTEGRATOR, COMPARATOR, BASEBAND I/O DRIVER, AND TRANSMIT/RECEIVE CONTROL LOGIC

The circuits for functions 27-32 of the transceiver 10 depicted in FIG. 1 are shown in FIG. 6. Adding a bypass capacitor C₁₃ to IC pin P, as shown in FIG. 6, converts transistor Q₄₂ in the time domain bandpass filter 24 of FIG. 5 and transistor Q₇₉ of FIG. 6 to a detector by integrating the asymmetric output. This integration must be fairly fast in order to minimize stretching of the carrier burst time interval. Subsequent symmetrical integration is provided by capacitor C₁₄ connected to IC pin Q which is supplied with a constant sourcing current of I_(B) by current mirror Q₁₂₂ and Q₁₂₃ from Q₇₈, as established by V_(B). The detector transistor Q₇₉ controls a sinking current of 2 I_(B) supplied by Q₇₆ and Q₇₇ in parallel. Thus, absence of signal charges capacitor C₁₄ at a rate set by I_(B), and presence of signal discharges C₁₄ at the same rate. The voltage on C₁₄ can swing from essentially zero (saturation of Q.sub. 76 and Q₇₇) to V_(CC) minus V_(BE) of Q₁₂₃ and V_(SAT) of Q₁₂₂. Since this swing is not symmetrical about V_(R), the voltage on C₁₄ is compared, by Q₇₃ and Q₇₅, with a reference that swings about 1/2 (V_(CC) -V_(BE)) established by Q₇₀, R₃₉, and R₄₀. Hysteresis of +/-2 volts about this reference is provided by R₄₁ with current from Q₁₂₀ or from Q₁₂₁ through current mirror Q₇₂ and Q₇₁ which comprise the hysteresis circuit 29 of FIG. 1.

Differential output current of the comparator 30 of FIG. 1 is reproduced by Q₁₁₉ and Q₆₉ and applied to the baseband I/O driver Q₆₅ and to T/R logic transistor Q₆₈ through resistors R₃₆ and R₃₇ respectively, as shown in FIG. 6. When carrier signal is absent, capacitor C₁₄ charges, raising the voltage at IC pin Q above reference, providing current in Q₇₅, Q₁₂₁, Q₇₂, Q₇₁ and Q₆₉, thus turning off Q₆₈ and Q₆₅. An external resistor R₂₀ connected to IC pin R can then pull the I/O port 11 to a positive voltage. This voltage at pin R applied to emitter follower Q₆₆ turns on T/R logic transistor Q₆₇. In the presence of carrier signal, C₁₄ discharges, reducing the voltage at IC pin Q below the changed reference voltage, causing current to switch to Q₇₃, Q₁₂₀ and Q₁₁₉ which turns on Q₆₅ and Q₆₈. Driver transistor Q₆₅ within the I/O driver 28 of FIG. 1 pulls I/O port 11 and IC pin R low which turns off Q₆₆ and Q₆₇ which comprise the T/R control logic NOR GATE 27.

In the receiving mode, the T/R control line 36 is being pulled down either by Q₆₇ when the baseband I/O port 11 is high (no carrier) or by Q₆₈ when the baseband I/O port is pulled low (by carrier). If the baseband I/O port 11 is pulled low externally, and not internally, both Q₆₇ and Q₆₈ are off and the T/R control line 36 is released.

GATED POWER AMPLIFIER

When the gated power amplifier 25 of FIG. 1 is turned on, a power oscillator is formed in combination with feedback through the dynamic limiter 16 which establishes oscillator amplitude, and the L/C narrow band filter 20 which determines the oscillation frequency and sinusoidal waveform.

Operating current for the gated power amplifier 25, shown in detail in FIG. 7, is provided from V_(CC) by resistor R₁₈ to IC pin T whenever the T/R control line 41 is released. Capacitor C₁₅ provides a few microseconds delay to allow for some capacitive loading on the baseband I/O port which causes a time delay between turn-off of T/R logic transistor Q₆₈ and turn-on of Q₆₇ in the transition from a received low state at IC pin R as best seen in FIG. 6.

When the baseband I/O port 11 is pulled low externally, the T/R control line 41 is released, the potential at IC pin T rises until Q₅₈ emitter current is sufficient to cause Q₅₉ to sink the current supplied by R₁₈. The potential at the emitter of Q₅₈ is then 2.0 V_(BE) of Q₅₉, as established by R₂₉ and R₃₀. This voltage creates a current through R₂₈ to drive Q₁₈ within the gated level detector 25 of FIG. 4 to inhibit the gated level detector, thereby blocking the receiving path.

The base-emitter voltage of Q₅₉ drives four other current sources--Q₅₂, Q₅₅, Q₅₇ and Q₆₁. Q₆₁ supplies operating current to the first-stage differential amplifier Q₆₀, Q₆₂ and Q₁₁₈ which has a voltage gain of 5, established by feedback resistors R₃₁ and R₃₂, for signal frequency appearing on the parallel resonant circuit L₁, C₈ at IC pin K.

The second stage amplifier, Q₅₆, Q₅₃, Q₁₁₇ and Q₅₂ operates at twice the emitter current of the first stage, supplied by Q₅₅ and Q₅₇ in parallel. The current differential of Q₁₁₇ and Q₅₂ drives the darlington "totem pole" output stage consisting of Q₄₉ and Q₅₀ driving the large 200 mA power transistors Q₄₃ and Q₄₄. Capacitor C₁₇ connected between pins B and V stabilizes the amplifier. Feedback resistors R₃ and R₄ set the noload voltage gain of this stage at 10, and short-circuit gain at 20. Resistors R₁ and R₂ provide current limiting during high amplitude transient voltages and the mid-point connection for feedback reduces the amplifier output impedance as partial compensation for these resistors.

In the receiving mode, with the T/R control logic pulling IC pin T low, the output impedance of the gated power amplifier 25 is established by R₃ and R₄ at 11 K ohms. High voltage transients coming in to the isolation transformer 13 are clamped, at lower current levels, by zener diodes Q₄₇ and Q₄₈ driving Q₄₅ and Q₄₆ and the power output transistors Q₄₃, Q₄₄. Diodes D₁ and D₂ provide transient clamping at higher current levels, as determined by R₁ and R₂ and the magnitudes of V_(CC), V_(EB) and V_(BE). Diode Q₅₄ clamps the base of Q₅₀ low in the receiving mode in order to prevent high frequency current in compensating capacitor C₁₇ from turning on the lower power output stage.

TRANSCEIVER IC

The transceiver circuit elements contained within the integrated circuit 40 are shown in FIG. 8 with IC pins A-V arranged for connection with the other components within the carrier current digital data transceiver circuit 10 depicted schematically in FIG. 2. All of the circuit elements shown in FIG. 8 and their operation have been described in detail earlier with reference to FIGS. 3-7, with like reference numerals.

Although the carrier current digital data transceiver of the invention is described for connecting between a power line communication system and a microprocessor data bus, this is by way of example only since the transceiver can communicate over any medium providing suitable carrier propagation, and with any source of baseband data, such as micro and mini computers. The transceiver integrated circuit is embodied within a 20 pin IC configuration. It is to be clearly understood that other IC configurations having a lesser number of terminal pins can also be employed depending upon user requirements and economics.

One such transceiver integrated circuit having a 14 pin IC configuration is shown at 41 in FIGS. 9 and 10. This is accomplished in part by placing resistors R₁₁ -R₁₄ external to the 20 pin integrated circuit 40 of FIG. 2 within the 14 pin integrated circuit. In addition, DC feedback in the dynamic limiter 16 shown in FIGS. 1 and 3 has been eliminated and current limiting resistors are added to the zener diodes Q₄₇ and Q₄₈ as best seen in FIG. 10. The high pass filter 23 between the frequency divider 22 and the time domain bandpass fiter 24 shown in FIG. 1 has been revised, adding transistor Q₁₂₄ and deleting transistor Q₂₄ seen by comparing the circuits shown in FIGS. 8 and 10. This simplification in circuitry is accomplished by using the characteristics of the fast integrator function of capacitor C₁₃ within the detector and integrator circuits depicted in FIGS. 1 and 6 to reset the time domain filter output flip flop Q₃₉ and Q₄₀ shown in FIG. 5 when, in the absence of signal, transistor Q₄₂ remains conducting longer than about 12 microseconds. Capacitor C₁₃ is discharged to a voltage low enough to turn on transistors Q₁₂₄ and Q₂₅. FIG. 9 also shows the use of an LC tuned circuit L₂ and C₆ for the wide band filter 15 of FIG. 1 as described earlier and shown as an RC filter C₄ -C₆ and R₉ -R₁₁ in FIG. 2.

Although the inventions have been described with reference to a specific embodiment thereof, numerous modifications thereof are possible without departing from the inventions and it is desirable to cover all modifications falling within the spirit and scope of these inventions. 

I claim:
 1. A transceiver providing an interface for digital data exchange between a baseband bus and a modulated carrier frequency braodband bus comprising:broadband input/output port means for coupling carrier frequency signals to and from a braodband bus; baseband input/output port means for coupling digital signals to and from a baseband bus; dynamic limiter means coupled to said broadband input/output port means for dynamically limiting carrier frequency signals received by said broadband input/output port means to a first predetermined level for all values of carrier frequency signals received at said input/output port means above a second predetermined level, said dynamic limiter means including a narrow band resonant filter tuned to said carrier frequency signals and providing an output for said dynamic limiter means; detector means connected to the output of said dynamic limiter means for detecting said carrier frequency signals and providing a baseband output signal, the output of said detector means being coupled to said baseband input/output port means; logic and gating means connected to said detector means and to said baseband input/output port means for selectively enabling and disabling transmitter and receiver functions within said transceiver depending on direction of digital data transfer between said broadband and baseband buses as determined by the output of said detector means and the logic level of said baseband input/output port means, said logic and gating means including a gated power amplifier having an output connected to said broadband input/output port means; and oscillator means including said resonant narrow band filter and operative when said transmitter function is enabled by said logic and gating means for providing carrier frequency signals to the input of said gated power amplifier for transmission on said broadband bus.
 2. The transceiver of claim 1 wherein said broadband input/output port means includes a first capacitor and a transformer connected to said broadband bus.
 3. The transceiver of claim 1 wherein said detector means includes means for integrating detected carrier frequency signals with substantially equal rise and fall time.
 4. The transceiver of claim 2 wherein said broadband input/output port means further includes a voltage surge suppressor connected betweeen said transformer and said dynamic limiter means.
 5. The transceiver of claim 3 further including a comparator wherein said integrated carrier signals are compared with a reference level for producing a rectangular digital waveform.
 6. The transceiver of claim 5 further comprising means for modifying the reference level of said comparator by an amount from said comparator to provide hysteresis in said comparator.
 7. The transceiver of claim 1 wherein said baseband input/output port means comprises an open collector driver connected to the output of said detector means to provide output detected carrier frequency signals.
 8. The transceiver of claim 1 further including a second filter connected to the output of said broadband input/output port means for selectively passing carrier frequency signals to said dynamic limiter means.
 9. The transceiver of claim 7 wherein said logic and gating means comprises a NOR gate having a pair of inputs connected to the input and output of said open collector driver and an output connected to said gated power amplifier.
 10. The transceiver of claim 8 wherein said second filter comprises an RC bandpass filter.
 11. The transceiver of claim 1 wherein said dynamic limiter means includes amplifier means and amplitude sensing means for controlling gain of said amplifier to establish said first predetermined level across said first filter.
 12. The transceiver of claim 11 wherein said amplifier comprises a variable transconductance amplifier.
 13. The transceiver of claim 11 wherein said amplitude sensing means comprises a dual polarity peak detector.
 14. The transceiver of claim 11 wherein said amplitude sensing means controls said amplifier gain through a low pass filter.
 15. The transceiver of claim 9 wherein said NOR gate output is connected to said oscillator.
 16. The transceiver of claim 1 wherein said logic and gating means includes gated threshold means intermediate said broadband input/output port means and said detector means for passing said carrier frequency signals having an amplitude exceeding a third predetermined level when said receiver function is enabled.
 17. The transceiver of claim 16 wherein said threshold means is connected to said detector means through a time domain band pass filter.
 18. The transceiver of claim 17 wherein said time domain band pass filter is connected to said threshold means through a frequency divider and a high pass filter.
 19. The transceiver of claim 2 wherein said transformer exhibits a magnetizing inductive reactance greater than an output impedance of said broadband bus for reducing attenuation of said carrier frequency signals when said transmitter is disabled.
 20. The transceiver of claim 2 wherein said transformer exhibits a leakage reactance comparable with reactance of said first capacitor at said carrier frequency to provide a series resonant circuit having an impedance lower than an input impedance of said broadband bus when said transmitter is enabled. 